1. Field of the Invention
This invention relates generally to the structure and fabrication process of trenched power DOMS transistors. More particularly, this invention relates to a novel and improved structure and process for fabricating a trenched power DMOS transistor provided with punch through prevention by applying a polysilicon layer to cover the trench corners to reduce the source dopant concentration in the corners where the trenches intersect.
2. Description of the Prior Art
The design and manufacture of a conventional trenched DMOS transistor are often limited by several technical difficulties. Specifically, the side wall damages caused by trench etching processes may affect the side wall oxide thickness and adversely affect the transistor performance. As a result of the weak points in the side wall oxide layer, particular design concerns arise which is related to a the punch through phenomena. A non-destructive leakage current in the channel region is induced due to the punch through. This problem more typically occurs at the sharp corners where two trenches intersect due to the difficulties in forming a uniform oxide layer on those spots and also the uneven diffusion process caused by the special geometric shapes at the corners.
A type of MOSFET transistor which applies double diffusion to form the active device regions is a DMOS transistor. It is also well known in the art to form trenches which is lined with thin layer of oxide and filled with conductive polysilicon to act as gate of the transistors. These types of transistors are often applied as power devices. In order to better understand the technical background of the present invention, the general device structure of a trenched DMOS transistor is first described. FIG. 1 is a cross-sectional view of a typical DMOS cell 10 in the core cell region which is supported on a N+ substrate 15 and an N- epi-taxial layer 20 formed on its top. The cell 10 includes a deep p-body region 25, a source region 30 wherein the source region 30 and the p-body region 25 surround a trenched gate 40 insulated by a gate oxide layer 35. The DMOS cell 10 is then covered with a PSG or BPSG protection layer 45 and connected externally with a gate contact 55, a source and body contact 50 and a drain contact 60. This device structure with the gate formed in a trench has the advantage that the cell density can be increased by shrinking the poly-gate length without the limitation, as that encountered in a planar DMOS, that the JFET resistance is increased when the gate poly length is reduced. The trenched DMOS transistors also have the additional benefits that the on-resistance is reduced as the result of higher cell density.
In U.S. Pat. No. 5,468,982 entitled "Trenched DMOS Transistor with Channel Block at Cell Trench Corners" (issued on Nov. 21, 1995), Hshieh et al., disclose a trenched DMOS transistor which applies a blocking photo-resist on the principle surface of the substrate to cover the areas where two trenches intersect during the source region implant. The corners where the trenches intersect are then blocked from forming channels therein. By blocking the corners at trench intersections, a cutout structure is generated at each trench corner such that the source regions do not extend to the trench corner. Instead the underlying body regions which are doped with opposite conductivity type extend to the trench corners. The problem of punch-through which is especially a problem with trenched DMOS transistors may be prevented. Puch-through which typically occurs at the channel region in the form of a leakage current prior to avalanche breakdown, tends to occur at the sharper corners, e.g., corners where two trenches intersect due to the crowding of the electric field lines with the corner curvature. With the cell structure as disclosed in the patented invention, the punch-through problems at the corners of trench intersections are eliminated.
For DMOS transistors of higher density, there is a disadvantage using the cell structure according to Hshieh et al. Referring to FIGS. 2A and 2B for the patented DMOS and the configuration of the blocking masks applied for carrying out the source implant operation. The small rectangular areas 142a, 142b, 142c, and 142a-1, are applied to block the center of each cell and blocks 142a-1, 142a-2, 142b-1, 142b-2, 142c-1, and 142c-2, etc., are applied to block the corners of the trench intersections. The length of the blocks 142a-1, i.e., d, is 3.5 micros, and the width of the blocks 142a-1 to 142c-2, i.e., e, is 1.7 microns. As the size of the cell shrinks, higher proportion of the trench areas, i.e., the areas 124a, 124b, . . . , and 124h, are now covered by the photo-resist areas used as source blocking. As more of the trenched poly gates are covered by the photo-resists for source blocking, the dopant concentration in the trenched poly is reduced as the doping ions are blocked in these covered areas. Reduction in dopant concentration in the trenched poly causes the conductive area to reduce. Thus, the sheet resistances in the trenched polycrystalline silicon are increased due to the reduced conductive areas in the trenched poly-gates. The speed of the device is adversary affected due to the higher poly sheet resistance.
Therefore, there is still a need in the art of power device fabrication, particularly for trenched power transistor design and fabrication, to provide a structure and fabrication process that would resolve these limitations.